Printed Circuit Board System Reverse Engineering Complexity

Printed Circuit Board System Reverse Engineering complexity is growing rapidly. As a result, current development costs can be staggering and are constantly increasing. As designers produce ever larger and more complex systems, it is becoming increasingly difficult to estimate how much time it will take to reverse engineering and verify these designs.

To compound this problem, system design cost estimation still does not have a quantitative approach. Although reverse engineering a system is very resource consuming, there is little work invested in measuring, understanding, and estimating the effort required.

To address part of the current shortcomings, this paper introduces µPCBComplexity, a methodology to measure and estimate PCB (printed circuit board) layout effort. PCBs are the central component of any system and can require large amounts of resources to properly design and verify.

µPCBComplexity consists of two main parts, a procedure to account for the contributions of the different elements in the design, which is coupled with a non-linear statistical regression of experimental measures. We use µPCBComplexity to evaluate a series of design effort estimators on several Printed circuit board systems reverse engineering projects. By using the proposed µPCBComplexity metric, designers can estimate Printed Circuit Board System Reverse Engineering effort.

This paper analyzes and proposes various statistics to estimate the layout effort required to develop PCBs. We investigate and quantify statistics such as area, component count, pin count and device types and sizes for many PCBs. We analyze several of these statistics, and propose a metric, obtained after applying non-linear regression over the different statistics, which we call µPCBComplexity. In addition, we provide insights on the correlation between several statistics and design effort for several known layout design times.