PCB Reverse Engineering Services

PCB Circuit Board Manufacture Capabilities

PCB CIRCUIT BOARD Manufacture Capability:

STANDARD
ADVANCED TECHNOLOGY
LEADING EDGE
PTH Through Hole Cu Plating Aspect Ratio
(PCB Thickness / Minimum Hole sizes)
6 to 1 8 to 1 10 to 1
Z axis Depth Drilled Cu Plating Aspect Ratio
(Z axis Thickness / Min Hole Sizes )
0.5 0.75 1 to 1
Drilled Hole size Minimum-Vias 0.010” dia 0.008” dia 0.006” dia
Outer Layer Via Land ( Pad) Size Minimum 0” dia 0”dia 0” dia
Inner Layer Via Land ( Pad) Size minimum . 0.026”dia 0.020”dia 0.018”dia
Plane Layer Via Relief (Antipad) Minimum 0.030” dia 0.024”dia 0.020”dia
Buried Via Land (Pad) Size Minimum 0”dia 0”dia 0”dia
Buried Via Holes Size – Sequential Lamination 0.0135”dia 0.010”dia 0.008”dia
Minimum Trace Width 0.005” 0.004” 0.003”
Minimum Line to Line Spacing**
(spacing should be 0.001”above the trace width)
0.005” 0.004” 0.004”
Drill Hole to Conductor up to 10 Layers 0.010” 0.008” 0.006”
Drill Hole to Conductor 12+Layers 0.012” 0.010” 0.008”
Layer to Layer registration Tolerance +/- 0.005” 0.004” 0.003”
Maximum PCB thickness 0.25” 0.25” 0.4”
Minimum Dielectric Thickness 0.005” 0.003” 0.0025”
PCB Edge to Conductor
( Except V score- See Spec )
0.015” 0.010” 0.005”
Electrical Test Minimum Component Pitch 0.010” 0.005” 0.004”
Solder mask Clearance per side 0.004” 0.003” 0.002”
Line to SMT Land Minimum space 0.006” 0.005” 0.004″
Base Cu Weights Minimum 1/2Oz 3/8 Oz 1/4 Oz
Average Layer Count >12 Layers 20 Layers 30 Layers
Average Panel Size 21” x 24” Usable Area: 19” x 22” (419.1mm x 571.5 mm)
Warp and Twist
( Design Dependent: Balanced or Unbalanced)
0.75% 0.75” 0.5”
Plated Through Holes Tolerance +/- 0.003” 0.0025” 0.002”
Impedance Tolerance +/- 10% 7% 5%
Copper Pour to Feature Spacing ( Outer ) 0.005” 0.004” 0.003”
Copper Pour to Feature ( Inner ) 0.005” 0.004” 0.003”

Tags: