Reverse Engineering Printed Circuit Boards

Reverse Engineering Printed Circuit Boards

Reverse Engineering Printed Circuit Boards

The resulting voltage drop is a gain error of 0.1/5 k (~0.0019%), well over 1 LSB (0.0015% for 16 bits). And this ignores the issue of the return path! It also ignores inductance, which could make the situation worse at high frequencies as a result of Reverse Engineering Printed Circuit Boards.

So, when dealing with precision circuits, the point is made that even simple design items such as printed circuit board trace resistance cannot be dealt with casually from Reverse Engineering Printed Circuit Boards. There are various solutions that can address this issue, such as wider traces (which may take up excessive space), and may not be a viable solution with the smallest packages and with packages with multiple rows of pins, such as a ball grid array (BGA), the use of heavier copper (which may be too expensive) or simply choosing a high input impedance converter.

But, the most important thing is to think it all through, avoiding any tendency to overlook items appearing innocuous on the surface. The gain error resulting from resistive voltage drop in printed circuit board signal leads is important only with high precision and/or at high resolutions (the Figure 12.3 example), or where large signal currents flow before Reverse Engineering printed circuit board. Where load impedance is constant and resistive, adjusting overall system gain can compensate for the error. In other circumstances, it may often be removed by the use of “Kelvin” or “voltage sensing” feedback.

In this modification to the case of Figure 12.3 a long resistive printed circuit board trace is still used to drive the input of a high resolution ADC, with low input impedance. In this case however, the voltage drop in the signal lead does not give rise to an error, as feedback is taken directly from the input pin of the ADC, and returned to the driving source. This scheme allows full accuracy to be achieved in the signal presented to the ADC, despite any voltage drop across the signal trace after PCB Reverse Engineering.