Printed Circuit Board Gerber Recreation

Printed circuit board gerber recreation effort keeps growing as additional constraints such as rising clock frequencies, reduced area, increasing number of layers, mixed signal devices, and the ever increase in component numbers and densities. All of these factors combined have led to a steady rate of increase in development costs for current systems. As we gerber recreation ever larger, denser and more complex systems, it is becoming increasingly difficult to estimate how much time would be required to gerber recreation and verify them. To compound this problem,

Printed circuit board gerber recreation effort estimation still does not have a quantitative approach. We present in this paper a first step toward creating a gerber recreation effort metric that is highly correlated with gerber recreation effort for PCB layout. We follow the same approach taken as the principles that are applicable to microprocessors are also applicable to PCBs. In this paper, gerber recreation effort corresponds to the number of engineering-hours required for implementation (layout) of a PCB gerber recreation.

Different gerber recreations have different constraints, leading to specific challenges; typical gerber recreation constraints being area, frequency, and cost. For example, having area being a primary gerber recreation constraint, may lead to a requirement for additional layers, more expensive package types, and more complex placement and routing. A gerber recreation constrained by cost, on the other hand, may require a balance between number of layers,area, drill density, types of packages and possibly the number of different drill sizes. Having clear constraints is necessary in estimating layout effort as it can drastically affect complexity.